The LCD Byte Driver is responsible for initializing the LCD Display on the Spartan3A Board and for Displaying Data on it.
SkolUart sends and receives Data over the Serial Connection.
SPI Initializer is responsible to set up the Preamplifier on the Spartan3A
The ADC Controller captures the ADC Data Board which is located in front of the ADC
The AdcRam stores the captured Data from the ADC.
The First Top Level FSM is responsible to start the ADC_Fsm.
The ADC_Fsm aquires Data and has included all Functionality to
Aquire a whole Data Frame and store it into RAM
Trigger Functionality
Sending Data back to Host
Makes correct TimeDomain (TimePerDiv - by dropping aquired data values.)
Protocol
Message Length : n (min: 7, max: 65541)
0
1
2
3
4
(5 ... n-2)
n-1
OpCode
MagicByte
DataBlockCount HighByte
DataBlockCount LowByte
DataBlockSize (Number of Bytes)
Data
CRC
1 Byte
1 Byte
1 Byte
1 Byte
1 Byte
0 to 65535 Bytes
1 Byte
Example Message
BE
EF
00
03
02
00 01
00 02
00 03
ff
OpCode
MagicByte
DataBlockCount HighByte
DataBlockCount LowByte
DataBlockSize (Number of Bytes)
Data
CRC
1 Byte
1 Byte
1 Byte
1 Byte
1 Byte
0 to 65535 Bytes
1 Byte
Has 3 Data Packets, with each size of 2bytes. OpCodes as JavaDoc
MagicByte is to determine correct MessageStart(in combination with opCode Range and DataBlockSize, which must be less than 4.)
DataBlockCount: Number of Blocks of Size DataBlockSize (Size 1 = 1 Byte, Size 2 = 2 bytes) in the Data Block.
CRC is for future usage
Protocol Requirements for FPGA Impl
Because the static HW Protocol Implementation of the Receiver, a fixed size of 7 data Bytes is needed. This means that always exact one data byte has to be sent to the FPGA. Even when the data Byte is useless.
Serial Port Settings
Baud Rate 115200
8 data Bits
1 stop Bit
No Flow Control
Fpga Settings
Current only the 50MHz Clock is used, and also most of the libraries are specialized for this Frequency.
