Aquires 152 Data Points per PictureFrame with a Sampling Rate of 1,5 MSamples per sec. (Fastest that onboard ADC can.)
Resolution can be changed (152,152*5 152*10 DataPoints). A maximum Resolution of 1k5 Samples is implemented now(limited by FPGA Size)
2 Channels.
Maximal Voltage Range of the Starter Board ADC Input: 400mV to 2900mV
Trigger at a specific Level
Trigger at positive edge or negative edge.
Different TimeDomains (TimePerDiv from 10us per Div to 50ms per Div).
Serial RS232 Communication at a BaudRate of 115200.
FPGA runs in polling mode. The Controller Gui requests every Data Frame seperately.
Single DataAquisition - one Voltage Value
Settings will be tested after sending to Device.
X & Y Axis Offset adjustable in Controller for each Channel
Features missing (so far) :
Faster ADC - Maybe begin of January
Input Voltage Range Adjustage
Known Issues:
TimePerDiv Error is about 5 Percent now. (Could not test further because of missing HW now)
Trigger Level not full tested
Dataaquisition has to be stopped before any Setting on the Device can take place (e.g. TriggerLevel, TriggerEdge, TimePerDiv etc.), and started afterwards.
skol_v0.3.1
Features implemented:
Aquires 152 Data Points per PictureFrame with a Sampling Rate of 1,5 MSamples per sec. (Fastest that onboard ADC can.)
2 Channels.
Maximal Voltage Range of the Starter Board ADC Input: 400mV to 2900mV
Trigger at a specific Level
Trigger at positive edge or negative edge.
Different TimeDomains (TimePerDiv from 10us per Div to 50ms per Div).
Serial RS232 Communication at a BaudRate of 115200.
FPGA runs in polling mode. The Controller Gui requests every Data Frame seperately.
Single DataAquisition - one Voltage Value
Settings will be tested after sending to Device.
Features missing (so far) :
Faster ADC - Maybe begin of January
Input Voltage Range Adjustage
Known Issues:
Trigger Level not full tested
Dataaquisition has to be stopped before any Setting on the Device can take place (e.g. TriggerLevel, TriggerEdge, TimePerDiv etc.), and started afterwards.
skol_v0.3.0
Features implemented:
Aquires 152 Data Points per PictureFrame with a Sampling Rate of 1,5 MSamples per sec. (Fastest that onboard ADC can.)
2 Channels.
Maximal Voltage Range of the Starter Board ADC Input: 400mV to 2900mV
Trigger at a specific Level
Trigger at positive edge or negative edge.
Different TimeDomains (TimePerDiv from 10us per Div to 50ms per Div).
Serial RS232 Communication at a BaudRate of 115200.
FPGA runs in polling mode. The Controller Gui requests every Data Frame seperately.
Single DataAquisition - one Voltage Value
Settings will be tested after sending to Device.
Features missing (so far) :
Faster ADC - Maybe begin of January
Input Voltage Range Adjustage
Known Issues:
Trigger Level not full tested
Osci Simulator broken
Dataaquisition has to be stopped before any Setting on the Device can take place (e.g. TriggerLevel, TriggerEdge, TimePerDiv etc.), and started afterwards.
skol_v0.2.2
Features implemented:
Aquires 152 Data Points per PictureFrame with a Sampling Rate of 1,5 MSamples per sec. (Fastest that onboard ADC can.)
Maximal Voltage Range of the Starter Board ADC Input: 400mV to 2900mV
Trigger at a specific Level
Trigger at positive edge or negative edge.
Different TimeDomains (TimePerDiv from 10us per Div to 50ms per Div).
Serial RS232 Communication at a BaudRate of 115200.
FPGA runs in polling mode. The Controller Gui requests every Data Frame seperately.
Single DataAquisition - one Voltage Value
Settings will be tested after sending to Device.
Features missing (so far) :
Faster ADC - Maybe begin of January
Input Voltage Range Adjustage
Send and Display Second Channel.
Known Issues:
Trigger Level not full tested
Mac OS X Application does not start :The executable flag is not set on "MacOsX/SkolController.app/Contents/MacOSJavaApplicationStub" The same for OsciDummy.
skol_v0.2.1
Features implemented:
Aquires 152 Data Points per PictureFrame with a Sampling Rate of 1,5 MSamples per sec. (Fastest that onboard ADC can.)
Maximal Voltage Range of the Starter Board ADC Input: 400mV to 2900mV
Trigger at a specific Level
Trigger at positive edge or negative edge.
Different TimeDomains (TimePerDiv from 10us per Div to 50ms per Div).
Serial RS232 Communication at a BaudRate of 115200.
FPGA runs in polling mode. The Controller Gui requests every Data Frame seperately.
Single DataAquisition - one Voltage Value
Features missing (so far) :
Faster ADC
Input Voltage Range Adjustage
Check Data after Setting, Reply from FPGA
Send and Display Second Channel.
LCD Display usage
Known Issues:
Trigger Level not full tested
skol_v0.2.0_rev_63
Features implemented:
Aquires 152 Data Points with a Sampling Rate of 1,5MegaSamples per sec. Data Points were reduced for TimePerDiv Function to work with rational values.
FPGA will is now running in polling mode. The Controller Gui requests every Data Frame seperately.
Trigger PosEdge NegEdge
Single DataAquisition - one Voltage Value
Trigger Level
Change Sampling Rate on the Fly (TimePerDiv)
Features missing (so far) :
LCD Display usage
Check Data after Setting, if it's ok
Known Issues:
Trigger Level not full tested
skol_v0.1.0_rev19
Initial release.
Prototype Status.
Features implemented:
Aquires 250 Data Points with a Sampling Rate of 1,5MegaSamples per sec
FPGA will is now running in polling mode. The Controller Gui requests every Data Frame seperately.